The present invention relates to a semiconductor device equipped with a central processing unit (CPU) which executes each instruction fetched from a memory, and is, for example, suitably used for a semiconductor device equipped with an instruction queue for temporarily storing a fetched instruction and an instruction cache for storing an instruction executed in the past.
Recently, a microprocessor system has increased a delay of memory access with improvements in its performance due to improvements in clock frequency and the like and has thus become a bottleneck of a system performance improvement. In order to reduce this delay, a common microprocessor system has hidden the delay of the memory access by being equipped with an instruction queue and/or a cache memory.
The instruction queue is capable of reducing a delay due to an instruction fetch by fetching (prefetching) an instruction in advance and holding it before a CPU decodes an instruction code. The cache memory is capable of reducing a delay in the case of access being made to the same address again by holding an instruction and data of an address accessed once in a small memory.
As a document that has disclosed a processor equipped with an instruction queue and a cache memory, there is cited, for example, a Patent Document 1. The processor of this document has further been provided with a branch prediction circuit that predicts a branch destination address from storage addresses of branch instructions.